1. Field of the Invention
The present invention relates to electronic circuits some elements of which need a clock supplying several clock signals having the same frequency and normally the same phase, and more particularly to a circuit that detects whether the skew between two clock signals is lower than a tolerable maximum limit.
2. Discussion of the Related Art
A large number of circuits include elements, such as flip-flops, counters, etc., which must be synchronized on a common clock signal. On an integrated circuit chip, several elements to be synchronized are distributed, so that the clock signal is provided to those elements through links of distinct lengths, some of the links being substantially longer than others. On an integrated circuit chip, the capacitance of a link increases with its length. A clock link is generally controlled by an amplifier providing a maximum current that is determined by the size of its transistors. Thus, the slope of the edges of a clock signal provided on a line increases with the maximum current of the amplifier and decreases with the length of the line (the line capacitance). A clock signal must exhibit steep edges. Accordingly, if the length of the clock lines is great, the output current of the amplifier must be increased. However, if the current in a line is increased beyond a specific limit, the section of the line must also be increased to prevent the line from being damaged. Generally, the increase in the line section is obtained by increasing the width of the conductors on the chip. This width increase is limited and is often incompatible with a large number of integrated circuit design systems since this increase causes, not only an increase of the chip surface area, but also problems for placing and routing the chip elements.
FIG. 1 represents a commonly used method for distributing a clock on an integrated circuit chip. The integrated circuit elements are grouped in several areas 10 having a compact shape (i.e., a shape that is rectangular or nearly square), so that the links inside these areas each have a length that is as short as possible. To each area 10 a distinct clock signal CK1, CK2, . . . is provided through a respective current amplifier 12. All amplifiers 12 receive a global clock signal CK0 provided by a clock generator 14 through an amplifier 16.
With this configuration, each clock signal CK1, CK2, . . . is provided to a line having a reduced length. Accordingly, to obtain clock signals with edges having a suitable slope, these clock lines do not need to be supplied with very high currents which would require increasing their width.
However, lines CK1, CK2, etc., generally have dissimilar lengths and accordingly dissimilar capacitances. Since amplifiers 12 have substantially identical characteristics, edges with dissimilar slopes are obtained on the clock lines. These dissimilar slopes cause phase-shiftings (skews) between the clock signals. As explained hereinafter, an excessive skew between two clock signals can be detrimental.
To reduce the skew, the shortest clock lines can be lengthened. This method not only complicates the integrated circuit design and increases the chip surface area, but also provides undetermined results depending upon the technology that is used to fabricate the integrated circuit.
Accordingly, a skew will still remain between the various clock signals, even if precautions are taken.
Shift registers are particularly sensitive to skews between the clock signals, when the flip-flops of the registers are in different areas 10, that is, when they are enabled by distinct clock signals.
FIG. 2 represents two D-type flip-flops 20 and 21 connected according to a shift register configuration. Flip-flop 20 is enabled, for example, by the clock signal CK1 and receives a signal to be shifted, for example from a preceding flip-flop, on an input D. Flip-flop 21 is enabled by the clock signal CK2, for example, and receives at its input D the output Q1 of flip-flop 20. In the following example, it is assumed that the input D of flip-flop 20 is at 0 and the outputs Q1 and Q2 are at 1 and 0, respectively.
In normal operation, the 0 at the input of flip-flop 20 is provided to the output Q1 and the 1 of output Q1 is provided to the output Q2 upon the substantially simultaneous occurrence of the two rising edges of signals CK1 and CK2.
FIG. 3A is a timing diagram illustrating the normal operation of the shift register of FIG. 2, in the worst case when the clock signal CK1 is in phase advance by a duration Ts with respect to the clock signal CK2.
At time t.sub.1, a rising edge of the clock signal CK1 occurs. The input D of the flip-flop 20 is at 0, the output Q1 of flip-flop 20 is at 1 and the output Q2 of flip-flop 21 is at 0. The flip-flop 20 reacts to this rising edge with a delay Tp referred to as a propagation time of the flip-flop. Thus, at time t.sub.3 =T.sub.1 +TP, the output Q1 switches to 0, which is the state present at the input D of flip-flop 20 at time t.sub.1.
In the meantime, at time t.sub.2 =t.sub.1 +Ts, a rising edge of the clock signal CK2 occurs. Like the flip-flop 20, the state of the output Q2 of the flip-flop 21 switches with some delay at time t.sub.4 =t.sub.2 +Tp. The output Q2 of flip-flop 21 goes to 1, which is the state present at the input of flip-flop 21 at time t.sub.2.
A flip-flop exhibits a so-called holding time Th corresponding to the minimum period during which a state must be maintained at the flip-flop input after its enable time so that this value is effectively taken into account (i.e., transmitted to the flip-flop output). If the signal is not maintained during time Th, the flip-flop erroneously operates. In the example of FIG. 3A, the holding time Th of flip-flop 21 is assumed to be sufficient, which means that Ts&lt;Tp-Th.
FIG. 3B represents an erroneous operation. With respect to the case of FIG. 3A, the skew Ts between the clock signals CK1 and CK2 is increased, so that Ts&gt;Tp-Th. At time t.sub.4, the output Q2 switches to the state taken by the output Q1 after time t.sub.3, that is the state is held at 0 instead of switching to 1; state 1 is lost.
In a test step of an integrated circuit after manufacturing, when a defect is detected, it is generally difficult to determine the cause of this defect. The defect may be caused by an excessive skew between the various clock signals, but this is difficult to accurately ascertain because the holding time Th of the flip-flop varies from one chip to the other and depends upon the technology that is used.